Implementation
Physical Implementation
- Synthesis for area & timing optimization
- SDC clean-up for constraint error fixes
- Static Timing Analysis — setup, hold, max transition & noise
- Simulation for functional verification
- Test vector generation
Non-Stop &
One-Time Success.
- Process
- 180nm — 7nm
- Scope
- Implementation · PD · DFT
- Based in
- Suwon, KR
AboutAn ASIC design partner
An ASIC design partner
for fabless & foundry.
StarChips was incorporated in September 2024 as a specialist in ASIC design.
We are a technology company specializing in ASIC design for fabless companies and foundries.
Our engineers bring deep experience across process nodes from 180nm to 7nm deep sub-micron, and we are committed to leading the ASIC design service market.
Through design partnerships with a broad network of domestic semiconductor companies, we strive to be the technology partner that delivers Non-Stop & One-Time Success to fabless IC customers.
As a companion to semiconductor design engineers and a leader in development and mass-production support, we aim to be the foundation for our customers' profit and growth.
- Process Nodes
- 180 → 7nm
- Established
- 2024.09
- Success Target
- One Time
180nm — 7nm · Deep Sub-Micron
ASIC Design FlowFrom Design Entry to GDS Out —
From Design Entry to GDS Out —
we own the full flow.
We execute the complete 12-step ASIC design flow consistently, from RTL entry to final GDS delivery.
- 01
Design Entry
Capture the design using a hardware description language (HDL) or schematic entry.
- 02
Logic Synthesis
Produce a gate-level netlist — logic cells and the nets connecting them.
- 03
DFT Implementation
Insert test logic for logic cells, memory, and IP.
- 04
Pre-layout Simulation
Verify the gate-level netlist functions correctly.
- 05
Floor Planning
Arrange the blocks of the netlist on the chip.
- 06
Placement
Decide the locations of cells within a block.
- 07
CTS
Insert buffers and inverters along the clock paths to balance clock delay.
- 08
Routing
Make the connections between cells and blocks.
- 09
Physical Verification
Ensure the layout works as intended — design rule check (DRC) and layout-versus-schematic (LVS).
- 10
IR-DROP
Check static and dynamic voltage drop across the power grid.
- 11
Post-layout Simulation
Confirm the design still works with the added loads of the interconnect.
- 12
GDS Out
Deliver GDS (Graphic Database System) to the process.
Our ServicesThree core services
Three core services
across the entire design flow.
Place & Route
Physical Design
- Floorplan for area reduction & macro-timing optimization
- Placement of standard cells
- Clock Tree Synthesis
- Routing for physical cell connections
- IR-DROP — static & dynamic power check
- RDL for bump design
- Physical Verification — DRC, LVS, ESD & antenna
DFT
Design For Test
- Clock generation for DFT
- IO MUX for DFT
- Scan insertion & verification to meet fault-coverage targets
- MBIST insertion & verification for memory test
- IP direct-access test for IP integration
Clients
Working with the world's leading process technologies.
We hold proven experience across many domestic semiconductor companies and global foundry processes.
ContactReady to start
Ready to start
your project?
We welcome ASIC design inquiries and partnership proposals. Feel free to reach out.
Address
#613, 237 Yeongtong-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic of Korea (Ace High-End Tower Yeongtong)
Tel
031-202-1277Fax
031-202-1288
